Hardware Trojan Localization: Modeling and Empirical Approach
© 2022 Springer Nature Switzerland AG
Abstract
This chapter presents mechanisms to localize Hardware Trojan (HT) in modern Integrated Circuit (IC) supply chain to ensure trustworthiness of computing infrastructure. We employ both analytical and estimation techniques to validate the localization. Our estimation framework is built upon characterizing technology mapped arithmetic module architectures. Such analysis does not require any golden design while simultaneously raises the abstraction to Register-Transfer Level (RTL). We present an analytical modeling technique that can identify rare activity region and complement traditional testing-based detection mechanism. Our experimental evaluation has been conducted on six adders and four multiplier architectures. On average, we observe less than 2% Mean Square Error (MSE) as we evaluate the architectures of different bit-width and correlations.