Electrical and Computer Engineering Faculty Publications and Presentations
Document Type
Conference Proceeding
Publication Date
2001
Abstract
We present an efficient cache scheme, which can considerably reduce instruction cache misses caused by procedure call/returns. This scheme employs N-way banks and XOR mapping functions. The main function of this scheme is to place a group of instructions separated by a call instruction into a bank according to the initial and final bank selection mechanisms. After the initial bank selection mechanism selects a bank on an instruction cache miss, the final bank selection mechanism will determine the final bank for updating a cache line as a correction mechanism. These two mechanisms can guarantee that recent groups of instructions exist in each bank safely. We have developed a simulation program by using Shade and Spixtools, provided by SUN Microsystems, on an ultra SPARC/10 processor. Our experimental results show that these schemes reduce conflict misses more effectively than skewed-associative caches in both C (up to 9.29% improvement) and C++ (up to 30.71% improvement) programs on L1 caches. In addition, they also allow for a significant miss reduction on Branch Target Buffers (BTB).
Recommended Citation
Yul Chu and M. R. Ito, "An efficient instruction cache scheme for object-oriented languages," Conference Proceedings of the 2001 IEEE International Performance, Computing, and Communications Conference (Cat. No.01CH37210), Phoenix, AZ, USA, 2001, pp. 329-336, doi: 10.1109/IPCCC.2001.918670.
Publication Title
Conference Proceedings of the 2001 IEEE International Performance, Computing, and Communications Conference (Cat. No.01CH37210)
DOI
10.1109/IPCCC.2001.918670
Comments
© IEEE. Original published version available at https://doi.org/10.1109/IPCCC.2001.918670