Theses and Dissertations

Date of Award


Document Type


Degree Name

Master of Science in Engineering (MSE)


Electrical Engineering

First Advisor

Mark Chu

Second Advisor

Heinrich Foltz

Third Advisor

Bin Fu


As computational systems become ever-more integral to daily life, so too does the importance of understanding how these complex systems work. For those unfamiliar with the underlying concepts, this can be a daunting task. In an effort to address such concerns, this paper presents a Node-RED based cache simulator that enables users to observe the effects of their desired cache configuration, with users having the ability to easily modify various parameters, such as the core count, the number of levels within the cache, and coherence protocols, among other parameters. Through the use of Node-RED, NRC-SIM allows for simplicity of use by providing web-based cache simulation to any web-connected device, including but not limited to, computers, laptops, and mobile devices. As such, users need only select their desired parameters, allowing the formatting for execution to be handled in the background. Node-RED’s modular, flow-based design enables the execution of NRC-SIM, allowing the user’s selected inputs to be manipulated in such a way that they are easily converted into the proper format. As NRC-SIM is a trace-driven cache simulator, various trace files have been collected from benchmark programs found in PARSEC and SPLASH2 through the use of Intel’s Pin, an open–source dynamic instrumentation tool framework. NRC-SIM’s experimental results show that it is a highly efficient, well-rounded cache simulator that generates results that are either comparable or an improvement over similar established cache simulators, such as SMPCache and SIMNCORE. As such, NRC-SIM can be an effective simulation tool for research purposes, or an educational tool that provides those less familiar with the concepts of cache memory an introduction into the subject matter.


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