Design for soft error tolerance in FPGA-implemented asynchronous circuits

Authors

Yu Bai, University of Texas-Pan American

Date of Award

7-2011

Document Type

Thesis

Degree Name

Master of Science (MS)

Department

Electrical Engineering

First Advisor

Dr. Weidong Kuang

Second Advisor

Dr. Hasina Huq

Third Advisor

Dr. Yul Chu

Abstract

This research in its present form is the result of experimentation on effect of soft error in FPGA-implemented asynchronous circuit. The conclusion are drawn that asynchronous circuit are much easier to detect soft error than synchronous circuits. The asynchronous circuit is implemented in FPGA with software fault injection method to analyze the behavior of soft error generation in FPGA implementation asynchronous circuits. The proposed detection circuit can detect all soft errors that generated in FPGA-implemented asynchronous circuit. The contributions include: investigation of FPGA structure, investigation of soft error model in FPGA, mechanism of FPGA implemented asynchronous circuit, behavior of soft error injection in FPGA look up table that implemented asynchronous circuit, and proposed detection scheme. The research on soft error injection in FPGA routing system and soft error rate estimation will be done in the future.

Comments

Copyright 2011 Yu Bai. All Rights Reserved.

https://www.proquest.com/dissertations-theses/design-soft-error-tolerance-fpga-implemented/docview/896957140/se-2?accountid=7119

Granting Institution

University of Texas-Pan American