Theses and Dissertations

Date of Award

12-2022

Document Type

Thesis

Degree Name

Master of Science (MS)

Department

Electrical Engineering

First Advisor

Dr. Mark Yul Chu

Second Advisor

Dr. Weidong Kuang

Third Advisor

Dr. Wenjie Dong

Abstract

The current trend in a processor design has moved from multicore to manycore (tens to hundreds, or more cores) to support more computational power based on parallelism. One of challenges is how to handle such large number of cores’ data in cache memories through an efficient inter-core communication and cache coherence. To meet the demand, this paper presents a manycore cache memory simulator for research and education purposes. The proposed simulator, called as SIMNCORE, is to design and evaluate various multi-level, such as L1 and L2, cache memories for manycore processing. The SIMNCORE will implement various trace files collected from parallel benchmark programs, such as PARSEC or SPLASH2, by using the Pin Tool. The Pin Tool, developed by Intel, is to generate the traces of benchmark programs by intercepting the execution of the instructions and surveilling memory addresses. Our experimental evaluation shows that the SIMNCORE is highly efficient in designing and evaluating manycore cache memories by comparing it with the other well-established simulators, such as SMPCache or FM-SIM. Therefore, we expect SIMNCORE can be an effective simulation tool to conduct cache memory-related studies for research related purposes.

Comments

Copyright 2022 Provashish Roy. All Rights Reserved.

https://go.openathens.net/redirector/utrgv.edu?url=https://www.proquest.com/dissertations-theses/simncore-multilevel-cache-memory-design-simulator/docview/2801814901/se-2?accountid=7119

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