Buffer Controlled Cache for Low Power Multicore Processors

Author

Marven Calagos, The University of Texas Rio Grande Valley

Date of Award

5-2018

Document Type

Thesis

Degree Name

Master of Science (MS)

Department

Electrical Engineering

First Advisor

Dr. Yul Chu

Second Advisor

Dr. Sanjeev Kumar

Third Advisor

Dr. John Abraham

Abstract

This thesis proposes a buffered dual access mode cache to reduce power consumption in multicore caches for embedded systems. This cache is called Buffer Controlled Cache (BCC cache). The proposed scheme introduces a pre-cache buffer to determine how to access the cache. The proposed cache shows better prediction rates and lower power consumption than conventional caches, such as Phased cache and Way-prediction cache. For single core implementation, Simplescalar and Cacti simulators have been used for these simulations using SPEC2000 benchmark programs. The experimental results show that the proposed cache improves the power consumption by 37%-42% over the conventional caches. Multi2Sim and McPAT simulators have been used for the multicore simulations using the Parsec benchmark programs. The experimental results show that the proposed cache improves the power consumption by as much as 54% over conventional caches.

Comments

Copyright 2018 Marven Calagos. All Rights Reserved.

https://www.proquest.com/dissertations-theses/buffer-controlled-cache-low-power-multicore/docview/2100708119/se-2?accountid=7119

Recommended Citation

Calagos, Marven, "Buffer Controlled Cache for Low Power Multicore Processors" (2018). Theses and Dissertations. 131.
https://scholarworks.utrgv.edu/etd/131