Theses and Dissertations
Date of Award
Master of Science (MS)
Dr. Yul Chu
Dr. Sanjeev Kumar
Dr. John Abraham
This thesis proposes a buffered dual access mode cache to reduce power consumption in multicore caches for embedded systems. This cache is called Buffer Controlled Cache (BCC cache). The proposed scheme introduces a pre-cache buffer to determine how to access the cache. The proposed cache shows better prediction rates and lower power consumption than conventional caches, such as Phased cache and Way-prediction cache. For single core implementation, Simplescalar and Cacti simulators have been used for these simulations using SPEC2000 benchmark programs. The experimental results show that the proposed cache improves the power consumption by 37%-42% over the conventional caches. Multi2Sim and McPAT simulators have been used for the multicore simulations using the Parsec benchmark programs. The experimental results show that the proposed cache improves the power consumption by as much as 54% over conventional caches.
Calagos, Marven, "Buffer Controlled Cache for Low Power Multicore Processors" (2018). Theses and Dissertations. 131.
Copyright 2018 Marven Calagos. All Rights Reserved.